Oxygen barrier for cell container process

ABSTRACT

A memory cell container of a DRAM semiconductor memory device and method for manufacturing the cell container. The cell includes a container formed in a structural layer such as borophosphosilicate glass. The container is then lined with a polysilicon such as hemispherical grained polysilicon. A dielectric layer is deposited over the polysilicon layer. A barrier layer is deposited over the dielectric layer such that the opening of the container is covered by not the sidewalls or the bottom of the container. The cell is then oxidize and the barrier layer provides protection as an oxygen barrier during the oxidation or any followed re-oxidation process.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to computer memorydevices and more specifically to capacitor cell containers formed insuch semiconductor memory devices.

[0003] 2. State of the Art

[0004] Computer memory devices, such as for example DRAM (dynamic randomaccess memory) semiconductor device modules, utilize a series or anarray of capacitors to store charge in retaining digital data forsubsequent recall. Each capacitor is coupled to a transistor andincludes a cell which holds a charge representative of a bit of data (i.e., a “1” or a “0”) depending on the charge of the cell. An array ofcapacitors, with a plurality of them holding a charge, allows fordigital information to be stored in compact and efficient manner whichmay be recalled by examining the charge on each capacitor. However, DRAMtype memory requires constant refreshing at a rapid rate due to leakagefrom the capacitors. Thus, one of the inherent inefficiencies of DRAMtype semiconductor device memory is the time and power utilized in thecontinual refreshing of the array of capacitors.

[0005] With the rapid advance in computer technology, DRAM semiconductordevice memory modules have been designed with a higher density of memorycells. While such density of memory cells has led to expanded capacityin a smaller package, it has also produced new design challenges. Forexample, regardless of how small or how dense a storage cell array ispackaged, each cell must hold a minimum amount of charge. Thus, in ahigh density memory cell array, the ability to retain the minimum levelof charge in a smaller volume memory needs to be addressed. One methodof addressing such an issue has been to increase the effective surfacearea of the memory cell, and thus the electrode associated with thememory cell.

[0006] An example of increasing the surface area of a capacitor memorycell container may be seen in drawing FIG. 1 which shows a prior artpartially fabricated memory cell within an integrated circuit such as aDRAM semiconductor memory device or chip. A conductive plug 10 locatedbetween neighboring word lines 12, usually comprising polysilicon, formselectrical contact with an active area 14 of a semiconductor substrate16. A planarized insulating layer 18, such as borophosphosilicate glass(BPSG) surrounds the word lines 12. The plug 10 is formed within anopening through the insulating layer 18. A structural layer 20 overliesthe insulating layer and may also be composed of BPSG or similarmaterial. A container 22 is formed in the structural layer, generally byanisotropically etching the structural layer 20 through a mask. Thecontainer 22 is generally a cylindrical cavity formed contiguous withthe conductive plug 10 and includes sidewalls 24 which extend to anopening in the structural layer 20. A layer 26 of hemispherical grained(HSG) silicon covers the interior surface of the container 22. The HSGlayer 26 increases the surface area of the cell container due to thehemispherical arrangement and patterning of the silicon. By increasingthe surface area of the memory cell container, and thus an associatedelectrode, capacitance charge may be increased for a generally smallercell container.

[0007] A thin layer of nitride 28 is deposited over the HSG layer 26 aswell as the surface of the structural layer 20. It is noted that thenitride layer 28 grows much thinner over the surface of the BPSGstructural layer 20 than on the HSG layer 26 due to the large nucleationincubation time of silicon nitride on BPSG. The slower growth of cellnitride on the BPSG layer 20 results in various problems. One problem isthat the thin layer of cell nitride 28 on the structural layer 20 failsto effectively block oxygen during processes such as oxidation orfollowed oxidation (reox). The inefficiency of the thin cell nitridelayer 28 allows oxygen to pass through the structural layer 20 resultingin the oxidation of the HSG polysilicon layer. Of course, the amount ofoxidation depends on the actual thickness of the nitride layer 26 abovethe structural layer 20. Additionally, the thin nitride layer allows forcurrent leakage at the edge of the container 22 thus creating anadditional inefficiency with regard to the operation of the capacitorcell structure.

[0008] In view of the shortcomings in the art, it would be advantageousto provide a memory cell structure and a method for forming such astructure that assists in preventing oxidation of the cell plate.Further it would be advantageous to provide a structure which is simpleto manufacture and a method which did not significantly interfere withexisting manufacturing processes. It would also be advantageous toprovide a memory cell structure and method for manufacturing thestructure to which reduced current leakage at the edge of the cellcontainer thus improving the overall efficiency of the memory cell.

BRIEF SUMMARY OF THE INVENTION

[0009] In accordance with one aspect of the invention a method offorming a cell container for the capacitor of a memory device, such as aDRAM semiconductor memory device or chip or module, is provided. Themethod includes forming a structural layer above a conductive plug. Acavity is formed in the structural layer, such as by etching. The cavityincludes at least one sidewall, such as a continual sidewall in acylinder, a bottom surface which is contiguous with the conductive plug,and an opening at the upper surface of the structural layer. A layer ofpolysilicon is deposited over the bottom and sidewall of the cavity. Adielectric, such as a nitride layer, is formed over the polysiliconlayer and at least a portion of the upper surface of the structurallayer including the area surrounding the opening of the cavity at theopening thereof. A barrier layer is deposited over at least a portion ofthe dielectric layer including the area surrounding the opening of thecavity and a portion of the sidewall adjacent the opening. The barrierlayer is deposited such that the majority of the sidewall as well as thebottom surface are not covered with the barrier layer. The container maythen be subjected to an oxidation process wherein the barrier layer isoxidized and acts as an oxygen barrier for the structural layer.

[0010] The structural layer may be formed of BPSG with the polysiliconlayer being formed of a hemispherical grained polysilicon to improve thesurface area of the cell container. The dielectric layer may be formedof silicon nitride. Aluminum is a suitable material for the barrierlayer and may be deposited by sputtering the aluminum on to help keepthe aluminum layer from substantially covering the interior cellsurface. Other metallic materials are also suitable such as, forexample, tantalum, zirconium, hafnium, tungsten, titanium or aluminumnitride. The formation of the metallic layer provides both, an oxygenbarrier for the cell structure during oxidation processes, as well asleakage protection for the cell at the opening edge.

[0011] In accordance with another aspect of the invention, a memory cellcontainer is provided. The memory cell includes a cavity formed in astructural layer such as BPSG. The cavity is formed to have a bottom,which is contiguous with a conductive plug, and a sidewall extendingfrom the bottom of the cavity to an opening at the upper surface of thestructural layer. A polysilicon layer, such as HSG polysilicon, isdeposited in the cavity on the bottom and along the sidewall. A nitridelayer, such as silicon nitride, is formed over the polysilicon layer andat least a portion of the upper surface of the structural layer. Abarrier layer, such as aluminum, covers at least a portion of thenitride above the structural layer and a small portion of the nitridealong the sidewall of the cavity adjacent the opening. The barrier layerforms an oxygen barrier for the cell container and also protects againstedge leakage during operation. As with the method, various materials maybe utilized to form the cell container, including various materialscited for the barrier layer.

[0012] In accordance with another aspect of the invention, a memorydevice is provided which includes a substrate having an array ofcapacitors formed therein. At least one of the capacitors includes acell container similar to that described above including the metalliclayer formed as an oxygen barrier.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0013] The foregoing and other advantages of the invention will becomeapparent upon reading the following detailed description and uponreference to the drawings in which:

[0014]FIG. 1 is a partial sectional view of a prior art cell containerof DRAM module; and

[0015] FIGS. 2A-2E show partial sectional views of a cell container fora DRAM module and a method of making such according to one aspect of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

[0016] Referring first to drawing FIG. 2A a cell container 40 is shownat an early stage of manufacturing. It is noted that manufacture of suchcells is carried out with respect to multiple cells and cell containers40 substantially simultaneously, however, for sake of clarity only onesuch cell container is depicted in the drawings. The cell container 40is formed above a conductive plug 10 and a planarized insulating layer18 similar to that previously discussed. However, for sake ofconvenience, various other components associated with the memory cellsuch as the word lines, active areas, or the semiconductor substrate arenot shown in drawing FIGS. 2A through 2E. To form the cell container 40,a structural layer 20, such as BPSG, is deposited above the planarizedinsulating layer 18 utilizing techniques and processes known by those ofskill in the art. A masked etching process then forms several openings,typically cylindrical in geometry, contiguous with the conductive plug10 and having sidewalls 24 which extend upwards therefrom.

[0017] As shown in drawing FIG. 2B, a layer of HSG polysilicon 26 isdeposited over the structural layer 20. The HSG layer 26 may be formedby various methods known in the art, including low pressure CVD (LPCVD)and silicon deposition followed by vacuum anneal under specifiedtemperature and pressure conditions. The HSG layer 26 may also be dopedfor greater conductivity. The formation of an HSG layer 26 is discussedin greater detail in U.S. Pat. No. 6,090,655 issued to Zahurak et al.,assigned to the assignee of the present invention and incorporated byreference herein. As discussed above, the HSG layer 26 provides a roughor textured surface thus increasing the surface area, as well as thecapacitance of the container 40. Grain size of the HSG layer may varydepending on the volume of the cell container 40 and the desired surfacearea of the container.

[0018] Subsequent the formation of the HSG layer 26, the structure maybe planarized for isolation of the memory cells on the array as shown indrawing FIG. 2C and thus again exposing the upper surface 42 of thestructural layer 20 in preparation for further processing. A dielectric28 is then deposited over the HSG layer 26 as well as the planarizedstructural layer 20 as seen in drawing FIG. 2D. The dielectric layer 28is conformally deposited according the methods and processes known tothose of skill in the art. It is contemplated that the dielectric layer28 is formed silicon nitride, such as Si₃N₄, however, it is noted thatother suitable dielectric materials may be utilized in conjunction withthe present invention such as, for example, oxynitride.

[0019] After the dielectric layer 28 has been deposited, a thin barrierlayer 44, such as aluminum, is deposited such that it covers thedielectric layer 28 above the upper surface 42 of the structural layer20 as well as partially into the cell container 40 about the rim 46 ofthe container 40. Such deposition may be accomplished by a low stepcoverage sputtering process after the dielectric layer 28 has beendeposited. Techniques such as low angle or high vacuum application maybe used in the sputtering process to ensure that the metallic layer isdeposited on the top part or rim area 46 of the container 40 withoutsignificantly depositing metal along the sidewalls or bottom surface ofthe container 40. While aluminum is contemplated for use as the metalliclayer, other metals may properly be utilized in conjunction with thepresent invention. For example, tantalum, zirconium, hafnium, tungsten,titanium, aluminum nitride, and their oxides may be used for the barrierlayer 44. It should be understood that the barrier layer 44 will form anoxygen barrier for those areas that it covers. To form the desiredoxygen barrier, the barrier layer can be formed by one of at least twomethods. The barrier layer 44 may be formed by directly sputtering ametallic layer to cover the dielectric layer 28 above the upper surface42 of the structural layer 20 as well as partially into the cellcontainer 40 about the rim 46 of the container 40 and then convertingthe metallic layer to a metallic oxide layer 44 by an oxidation process.When the metallic layer 44, a conductive layer, is converted byoxidation from a metallic layer 44 to a metallic oxide layer 44, themetallic oxide layer 44 becomes an insulation layer and is no longerconductive. If the barrier layer 44 is to be formed as a metallic oxidelayer in-situ, such a metallic oxide layer 44 may be formed by thereactive sputtering of metal in an oxidizing ambient atmosphere. Ineither event, whether the layer 44 is either sputtered and thenconverted to a metallic oxide layer by an external oxidation process oris formed in-situ by the reactive sputtering of a metal in an oxidizingambient atmosphere, the resulting metallic oxide layer 44 has a higherdielectric constant than that of silicon nitride. Therefore, theformation of the metallic oxide layer 44 does not affect the electricalperformance of the capacitor cell container 40 but, rather, functions asan oxygen diffusion barrier regarding the surrounding areas that themetallic oxide layer 44 covers after formation to prevent the diffusionof oxygen thereinto. When the metallic layer 44 is deposited as a metaland subjected to an external oxidation process, the metallic layer 44the cell container 40 is oxidized at relatively low temperatures in anoxidizing ambient, such as O₂, O₃, N₂O or H₂O with or without the aid ofplasma enhancement. Thus, for example, deposited aluminum 44 would beoxidized to form aluminum oxide (Al₂O₃). The aluminum oxide may also beformed after the aluminum layer 44 is deposited during a followed cellnitride re-oxidation step thus eliminating the need for an extraoxidation step. Subsequent oxidation of the metallic layer 44 convertsthe metallic layer 44 to a metallic oxide layer which has a highdielectric constant and preferably higher than the nitride layer 28 uponwhich it is deposited. Additionally, it is expected that the resultingthickness of oxidized metallic layer 44 be in the range of approximately20-200 Å.

[0020] The existence of the barrier layer 44 allows for oxidation of thecell container 40, including the nitride layer 28, to take place withoutoxygen leaking through the structural layer 20. As noted previously,oxygen leaking through the structural layer 20 would result in damage ofthe bottom cell layer such as the HSG layer 26. Furthermore, the barrierlayer 46 serves as a barrier of current leakage through the edge or rimarea 46 of the container 40 thus improving the efficiency of the cellcontainer in operation.

[0021] It is noted that while sputtering of the barrier layer 44 allowsfor deposition of the material in a manner which does not sufficientlyform an extraneous layer within the cell container itself (i.e., thecell walls and floor) formation of such would not be detrimental to theoperative capacity or does not affect the operative characteristics ofthe memory cell using cell container 40. The barrier layer 44 has nodiscernable or minimum impact, in any at all, upon cell capacitance inthe case that limited material is formed within the cell container 40itself. Further, the limited material falling into the cell containerwill be converted into a metallic oxide in the oxidation step orprocess. As such, the metallic oxide layer of material for the metalsdescribed herein will have a higher dielectric constant than the siliconnitride and, therefore, will have little effect on the capacitorelectrical performance.

[0022] A conductive top electrode layer 48 is deposited in the container40 and above the metallic layer 44 to form the resulting capacitivememory cell 50. The top electrode layer 48 may be formed, for example,of polysilicon, titanium nitride or even a silicide according toprocesses understood by those of skill in the art.

[0023] While the invention may be susceptible to various modificationsand alternative forms, specific embodiments have been shown by way ofexample in the drawings and have been described in detail herein.However, it should be understood that the invention is not intended tobe limited to the particular forms disclosed. Rather, the invention isto cover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the followingappended claims.

What is claimed is:
 1. A method of forming a cell container for a memorydevice comprising: providing a structural layer; forming a cavity in thestructural layer having a bottom and at least one sidewall extending toan opening at a surface of the structural layer; depositing apolysilicon layer over the bottom and at least one sidewall of thecavity; depositing a nitride layer over the polysilicon layer and atleast a portion of the surface of the structural layer including an areasurrounding the opening of the cavity; and depositing a barrier layerover at least a portion of the nitride layer including the areasurrounding the opening of the cavity and a portion of the at least onesidewall adjacent the opening.
 2. The method of claim 1, whereindepositing a barrier layer includes: depositing aluminum over at least aportion of the nitride layer.
 3. The method of claim 2, whereindepositing aluminum includes: sputtering the aluminum above the surfaceof the structural layer.
 4. The method of claim 3, further comprising:oxidizing the cell container including the sputtered layer of aluminum.5. The method of claim 1, wherein depositing a barrier layer includes:sputtering tantalum above the surface of the structural layer.
 6. Themethod of claim 5, further comprising: oxidizing the cell containerincluding the sputtered layer of tantalum.
 7. The method of claim 1,wherein depositing a barrier layer includes: sputtering hafnium abovethe surface of the structural layer.
 8. The method of claim 7, furthercomprising: oxidizing the cell container including the sputtered layerof hafnium.
 9. The method of claim 1, wherein depositing a barrier layerincludes: sputtering tungsten above the surface of the structural layer.10. The method of claim 10, further comprising: oxidizing the cellcontainer including the sputtered layer of tungsten.
 11. The method ofclaim 1, wherein depositing a barrier layer includes: sputteringtitanium above the surface of the structural layer.
 12. The method ofclaim 11, further comprising: oxidizing the cell container including thesputtered layer of titanium.
 13. The method of claim 1, whereindepositing a barrier layer includes: sputtering aluminum nitride abovethe surface of the structural layer.
 14. The method of claim 1, furthercomprising: oxidizing the cell container including the sputtered layerof aluminum nitride.
 15. The method of claim 1, wherein providing astructural layer includes: forming a borophosphosilicate glassstructural layer.
 16. The method of claim 1, wherein depositing apolysilicon layer includes: depositing a hemispherical grainedpolysilicon layer.
 17. The method of claim 1, wherein depositing anitride layer includes: depositing a silicon nitride layer.
 18. Themethod of claim 1, wherein depositing a barrier layer includes:sputtering an aluminum layer.
 19. The method of claim 18, furthercomprising: oxidizing the cell container; and forming aluminum oxide ofthe sputtered aluminum layer.
 20. The method of claim 19, furthercomprising: forming an electrode in the cavity.
 21. The method of claim1, further comprising: forming an electrode in the cavity.
 22. A methodof forming a cell container for a memory device comprising: providing astructural layer of borophosphosilicate glass; forming a cavity in thestructural layer having a bottom and at least one sidewall extending toan opening at a surface of the structural layer; depositing ahemispherical grained polysilicon layer over the bottom and at least onesidewall of the cavity; depositing a layer of silicon nitride over thehemispherical grained polysilicon layer and at least a portion of thesurface of the structural layer including an area surrounding theopening of the cavity; sputtering a layer of aluminum over at least aportion of the silicon nitride layer including the area surrounding theopening of the cavity and a portion of the at least one sidewalladjacent the opening; and oxidizing at least the aluminum layer to formaluminum oxide.
 23. A method of forming a cell container for a memorydevice comprising: providing a structural layer; forming a cavity in thestructural layer having a bottom and at least one sidewall extending toan opening at a surface of the structural layer; depositing apolysilicon layer over the bottom and at least one sidewall of thecavity; depositing a nitride layer over the polysilicon layer and atleast a portion of the surface of the structural layer including an areasurrounding the opening of the cavity; and depositing a barrier materialover at least a portion of the nitride layer including the areasurrounding the opening of the cavity and a portion of the at least onesidewall adjacent the opening, the barrier material having a higherdielectric constant than that of the nitride layer.
 24. A memory cellcontainer comprising: a cavity formed in a structural layer, the cavityhaving a bottom and at least one sidewall extending from the bottom toan opening in a surface of the structural layer; a polysilicon layercovering the bottom and at least one sidewall of the cavity; a nitridelayer covering the polysilicon layer and at least a portion of thesurface of the structural layer; and a barrier layer covering a portionof the nitride layer including an area around the opening of the cavityand partially along the sidewall within the cavity.
 25. The memory cellcontainer of claim 24, wherein the nitride layer includes siliconnitride.
 26. The memory cell container of claim 24, wherein thepolysilicon layer includes a hemispherical grained polysilicon.
 27. Thememory cell container of claim 24, wherein the structural layer includesborophosphosilicate glass.
 28. The memory cell container of claim 24,wherein the barrier layer includes aluminum oxide.
 29. The memory cellcontainer of claim 24, wherein the barrier layer includes tantalum. 30.The memory cell container of claim 24, wherein the barrier layerincludes zirconium.
 31. The memory cell container of claim 24, whereinthe barrier layer includes hafnium.
 32. The memory cell container ofclaim 24, wherein the barrier layer includes tungsten oxide.
 33. Thememory cell container of claim 24, wherein the barrier layer includestitanium oxide.
 34. The memory cell container of claim 24, wherein thebarrier layer includes aluminum nitride.
 35. The memory cell containerof claim 24, wherein the barrier layer comprises a metallic oxide layerhaving a higher dielectric constant than the nitride layer.
 36. Thememory cell container of claim 24, wherein the barrier layer is asputtered layer.
 37. The memory cell container of claim 24, wherein thebottom of the cavity is contiguous with a conductive plug.
 38. A memorydevice comprising: a substrate; an array of capacitors formed in thesubstrate, at least one the capacitors including a cell containercomprising: a cavity formed in a structural layer, the cavity having abottom and at least one sidewall extending from the bottom to an openingin a surface of the structural layer; a polysilicon layer covering thebottom and at least one sidewall of the cavity; a nitride layer coveringthe polysilicon layer and at least a portion of the surface of thestructural layer; and a barrier layer covering a portion of the nitridelayer including an area around the opening of the cavity and partiallyalong the sidewall within the cavity.
 39. The memory device of claim 38,wherein the nitride layer includes silicon nitride.
 40. The memorydevice of claim 39, wherein the polysilicon layer includes ahemispherical grained polysilicon.
 41. The memory device of claim 40,wherein the structural layer includes borophosphosilicate glass.
 42. Thememory device of claim 38, wherein the barrier layer includes aluminumoxide.
 43. The memory device of claim 38, wherein the barrier layerincludes tantalum.
 44. The memory device of claim 38, wherein thebarrier layer includes zirconium.
 45. The memory device of claim 38,wherein the barrier layer includes hafnium.
 46. The memory device ofclaim 38, wherein the barrier layer includes tungsten oxide.
 47. Thememory device of claim 38, wherein the barrier layer includes titaniumoxide.
 48. The memory device of claim 38, wherein the barrier layerincludes aluminum nitride.
 49. The memory device of claim 38, whereinthe barrier layer comprises a metallic oxide layer having a higherdielectric constant than the nitride layer.
 50. The memory device ofclaim 38, wherein the barrier layer is a sputtered layer.
 51. The memorydevice of claim 38, wherein the bottom of the cavity is contiguous witha conductive plug.